1. Field of the Invention
The present invention relates to the art of controllers for mechanical systems requiring logic processing of input data.
The invention is particularly related to a programmable controller equipment associated with a transfer line or to control a machine tool or other mechanical system of the type generally, in the prior art, controlled by a relay logic system.
2. Description of the Prior Art
One example of the prior art is U.S. Pat. No. 3,827,030 to Seipp. The Seipp reference discloses a programmable logic controller which incorporates, in addition to the normal input and output interface circuits, a supplemental random access memory for storing data used in calculating. Logic signals to and from the input and output interface circuits travel on separate one bit data buses. The data processed by the controller and retained in the random access memory is not significantly affected by power interruptions since a separate battery is incorporated into this circuit to maintain a holding voltage on the random access memory during such times as when the equipment is turned off or power is otherwise interrupted to the controller. While there are desirable aspects to a permanent memory, there are other desirable features of a nonpermanent memory for the temporary storage of data. Oftentimes the need arises to readily erase the data in a permanent memory and this can be difficult to accomplish with conventional controllers such as is set forth in Seipp.
In column 15 of U.S. Pat. No. 3,944,984 to Morley et al. reference is made to latch circuits which allow designated outputs to have retentive memory in case of power failure. While this is a desirable feature, programming of the device is made difficult by the dedication of the specific inputs and outputs to the latching functions when it may actually be that the data which is desired to be latched to the event of power failure does not need to interface to any equipment without further processing. Moreover, the resetting of the otherwise permanent memory found in certain prior art controllers is generally either so easy to do that it can be accomplished by accident or so difficult to do that substantial time is devoted to what should otherwise be a simple straightforward procedure.
In general, prior art controllers do not have associated with them switches and displays which make it easy for an operator to follow the functioning of the programmable controller and to determine where errors may exist in programs. Typically, prior art controllers require complex programming devices to be associated with them for the purpose of programming the read only memory generally used to store the program for the controller. For the most part, programmable logic controllers of the prior art do not have a display for displaying the state of the accumulator or the state of an accessed data bit nor do the devices have manual controls which are simple to operate in a manual mode or in a mode in which the outputs are disabled.
U.S. Pat. No. 4,006,464 to Landell discloses an industrial process sequence controller which digitally displays the sequence step. This patent also discloses a switch for disconnecting load terminals from attached loads thereby disabling the outputs and another switch for causing the sequence steps to be sequenced manually. However, this disclosure sets forth no means of protection which would preclude the energization of the loads when the unit is placed in the manual or set-up mode. This would permit inadvertent operation of the equipment in a fashion which could severely damage the equipment to which the controller is attached. The sequence controller of Landell does not incorporate a large programmable read only memory which is scanned at a high rate of speed as in prior art programmable logic controllers, and therefor it does not present the same programming difficulties of prior art programmable logic controllers.
Typically, programmable logic controllers of the prior art, such as U.S. Pat. No. 3,827,030 to Seipp, transferred data to the interface devices on a single bit data bus. Some prior art equipment incorporated a single bit data bus for transmitting data to the interface devices and a second single bit data bus for transmitting data back from the interface devices.
U.S. Pat. No. 3,881,172 to Bartlett et al. discloses a single bit data bus which is bidirectional and is used for both inputs and outputs.
U.S. Pat. No. 3,997,879 to Markley et al incorporates a complex data transfer system. An eight conductor data bus is used for transmitting data in parallel form to the interface devices. A second eight bit data bus is used to transmit data from the interface devices back to the processing equipment. Very complex and expensive equipment is required in the disclosed circuitry to handle the two eight bit data buses.
U.S. Pat. No. 3,827,030 to Seipp discloses a conditional instruction referred to as a "store Seipp function". This is used to allow the skipping of program statements prior to the next store instruction conditioned upon the state of the accumulator output. While this is a useful feature, certain programming needs make the use of this feature rather awkward. Occassionally, it is useful to be able to return to the beginning of the series of program statements with a single instruction rather than to have to use a sequence of skipping instructions to skip groups of operations between sequential store operations.
On function typically required to be performed either by a programmable logic controller or equipment associated with it is a timing function. Some programmable logic controllers incorporate complex timing circuits which can be numerically controlled by data programmed into the controller. Where read only program memories are used, this makes a change of the timing intervals difficult. In any event, the incorporation of this feature substantially increases the requirement for data storage by the data controller. Various attemps to incorporate timers into programmable controllers have generally resulted in very expensive equipment operating in a complex fashion. As an alternative to incorporating timers within the unit, timers can be connected to individual input and output circuits. Not only does this use up various address locations which thereby reduces the number of address locations available for normal input and output functions, but additionally (unless the circuit is otherwise specially designed), this uses expensive input and output interface circuitry for accomplishing the timing function.
Prior art controllers, such as disclosed in Seipp, require substantial decoding circuitry to convert the programmed data to operating instructions and to thereafter operate upon addressed data. This circuitry adds to the cost of the equipment, increases its size and reduces reliability. Similarly, machine instruction decoding has been complicated in prior art controllers, with similar effects.